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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16821
2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
Product Features
PI74AVC+16821 is designed for low-voltage operation, VCC = 1.65V to 3.6V True 24mA Balanced Drive @ 3.3V IOFF supports partial power-down operation 3.6V I/O Tolerant Inputs and Outputs All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay Industrial operation: 40C to +85C Available Packages: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K)
Description
Pericom Semiconductors PI74AVC+ series of logic circuits are produced using the Companys advanced submicron CMOS technology, achieving industry leading speed. The PI74AVC+ 16821is a 20-bit bus interface flip-flop designed for 1.65V to 3.6V VCC operation. It can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (HIGH or LOW level) or a highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.
Logic Block Diagram
1
1OE 2OE
28
1CLK 56
One of Ten Channels
2CLK 29
One of Ten Channels
1Q1
C1
1D
1D1 55
2
C1
1D
2D1 42
15
2Q1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
Pin Description
Pin Name OE CLK Dx Qx GND VCC D e s cription O utput Enable Input (Active LO W) Clock Input (Active HIGH) Data Inputs 3- State O utputs Ground Power
Truth Table(1)
Inputs OEn L L L H CLK H OR L X D H L X X Outputs Qn H L Q0 Z
Pin Configuration
1QE 1Q1 1Q2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1D1 1D2
Note: 1. H L X Z n
= = = = = =
High Signal Level Low Signal Level Irrelevant High Impedance LOW-to-HIGH Transition 1,2
GND
1Q3 1Q4
GND
1D3 1D4
VCC
1Q5 1Q6 1Q7
VCC
1D5 1D6 1D7
GND
1Q8 1Q9 1Q10 2Q1 2Q2 2Q3
GND
1D8 1D9 1D10 2D1 2D2 2D3
56-Pin A, K
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
VCC
2Q7 2Q8
VCC
2D7 2D8
GND
2Q9 2Q10 2OE
GND
2D9 2D10 2CLK
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................................................ 0.5V to +4.6V Input voltage range, VI ................................................................... 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) .............................. 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................................................ 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ...................................................... 50mA Output clamp current, IOK (VO <0) ................................................. 50mA Continuous output current, IO ..................................................................... 50mA Continuous current through each VCC or GND ............................ 100mA Package thermal impedance, JA(3): Package A ............................64C/W Package K ........................... 48C/W Storage Temperature range, Tstg ................................................. 65C to 150C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
M in. VCC VIH Supply Voltage High- level Input Voltage Operating Data retention only VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VIL Low- level Input Voltage VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VI VO IOH Input Voltage Output Voltage High- level output current Active State 3- State VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V IOL Low- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V DtDv Input transition rise or fall rate TA Operating free- air temperature VCC = 1.65V to 3.6V 40 0 0 0 1.65 1.2 VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 6 12 24 6 12 24 5 85 ns/V C mA V M ax. 3.6 Units
Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation.
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA =40C +85C)
Parame te rs VOH IOH = 100A IOH = 6mA IOH = 12mA IOH = 24mA VOL IOL = 100A IOL = 6mA IOL = 12mA IOL = 24mA II IOFF IOZ ICC CI Control Inputs Data Inputs CO Outputs VO = VCC or GND Control Inputs VI = VCC or GND VI or VO = 3.6V VI = VCC or GND VO = VCC or GND VI = VCC or GND IO = 0 VIH = 0.57V VIH = 0.7V VIH = 0.8V VIH = 1.07V VIH = 1.7V VIH = 2V Te s t Conditions (1) VCC 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V
Note: 1. Typical values are measured at TA = 25C.
M in. VCC 0.2V 1.2 1.75 2.0
M ax.
Units
0.2 0.45 0.55 0.8 2.5 10 10 40 4 4 6 6 8 8
V
A
pF
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
Timing requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V M in. fclock Clock frequency tw tsu th Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 4.1 1.7 2.7 1.3 3.1 2.1 1.0 M ax. VCC = 1.5V 0.1V M in. VCC = 1.8V 0.15V M ax. 160 2.5 1.5 1.0 VCC = 2.5V 0.2V M in. M ax. 200 2.5 1.4 1.0 VCC = 3.3V 0.3V M in. M ax. 200 ns Units
M ax. M in.
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parame te rs fmax tpd ten tdis
From (Input) CLK OE OE
To (Output) Q Q Q
VCC = 1.2V Typ. 6.8 6.8 5.4
VCC = 1.5V 0.1V M in. 1.5 1.6 2.5
VCC = 1.8V 0.15V M ax. 4.0 4.0 3.6 160
VCC = 2.5V 0.2V M in. 200 0.8 0.9 1 3.2 3.3 3.4 M ax.
VCC = 3.3V 0.3V M in. 200 0.7 0.7 1.5 2.8 3.0 3.4 ns M ax. Units
M ax. M in. 4.5 4.5 4.2 1.2 1.6 2.3
Operating Characteristics, TA= 25C
VCC = 1.8V 0.15V Parame te rs Cpd Power Dissipation Capacitance O utputs Enabled O utputs Disabled Te s t Conditions CL = 0pF, f = 10 MHz Typical 90 66 VCC = 2.5V 0.2V Typical 100 72 VCC = 3.3V 0.3V Typical 110 78 Units pF
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V
2xVCC From Output Under Test CL = 15pF
(See Note A)
2
S1
Open GND
Te s t
2
S1 O pen 2 x VCC GND
tpd tPLZ/tPZL tPHZ/tPZH
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V tPHZ VCC/2 VOH -0.1V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
1 k 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
2k 1
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.15V tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
2xVCC From Output Under Test CL =30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.15V tPHZ VCC/2 VOH -0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
VCC Timing Input VCC/2 0V tsu th
tW VCC Input VCC/2 VCC/2 0V
VCC
Data Input
VCC/2
VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.3V tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs
56-pin TSSOP (A) Package
56
.236 .244
6.0 6.2
1
.547 .555
13.9 14.1 1.20 .047 Max. SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
.0197 BSC 0.50 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.007 .011 0.17 0.27
.002 .006 0.05 0.15
56-pin TVSOP (K) Package
56
.169 .177
4.30 4.50
0.09 0.20 .0035 .008
1 .031 .041 0.80 1.05
0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .047 1.20 Max.
.441 .449
11.20 11.40
.016 BSC 0.40 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS
.005 .009 0.13 0.23
.002 .006 0.05 0.15
Ordering Information
Orde ring D ata PI74AVC+16821A PI74AVC+16821K D e s cription 56- pin, 240- mil wide plastic TSSO P 56- pin, 173- mil wide plastic TVSO P
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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